1. Field of the Invention
The present invention relates to a display driver IC (integrated circuit) using a serial interface and also relates to an electronic device using the display driver IC.
2. Description of Related Art
Recent high integration of a single chip micro-controller has enabled many peripheral ICs to be controlled by the single chip micro-controller. An unrestricted increase in the number of the terminals of the single chip micro-controller is not permitted for reasons peculiar to each peripheral IC and hence there is a physical restriction on the number of terminals permitted within the range of the chip size. For these reasons, serial transmission is made between the single chip micro-controller and the peripheral ICs to thereby reduce the number of mutual terminals.
As a serial transmission system of this type, an I2C bus is known. This I2C (Inter-Integrated Circuits) bus includes only two bus lines, namely, a bidirectional serial data line (SDA) and a serial clock line (SCL) with the intention of establishing effective mutual control between ICs.
FIG. 6 shows the original I2C bus protocol. One byte information following a start condition bit S consists of a slave address and a read/write designation bit. A slave address is a specific address for identifying a plurality of slave ICs connected to a bus of a single chip micro-controller which is a master.
Command data, display data and the like are transmitted in byte units subsequent to the one byte information including a slave address, as shown in FIG. 6. Each byte must be followed by an acknowledge bit A from a slave.
In FIG. 6, this one byte information which follows the one byte information including the slave address consists of a continuation bit C of one byte and command data of 7 bits. If the continuation bit C=0, this means that the data of 7 bits following the bit C is final command data, and if C=1, this means that other command data will further continue in one byte units. Then if necessary, display data is sent in byte unit after the final command data, and finally a stop condition bit P which is sent after an acknowledge bit terminates the transmission.
In the I2C bus protocol shown in FIG. 6, only 7 bits can be used for the command data since 1 bit in 1 byte is used as a continuation bit C. A technique in which a high order bit in data of one byte is used for another function in the above manner is also disclosed in Japanese Patent Application Laid-Open No. 7-13913. In this patent application, high order two bits in 1-byte serial data have a function of controlling the state of peripheral circuits, for example.
The I2C bus protocol shown in FIG. 7 and FIG. 8 is developed to make it possible to send command data of one byte or more.
Subsequent to the one byte information including a slave address and to an acknowledge bit A, two bytes information including a control byte and command data is sent, as shown in FIG. 7. Command bits of low order 8 bits in the latter command data and the remainder of the high order command bits in the former control byte enable to output command data comprising data of one byte (8 bits) and more. It is to be noted that the highest order bit C0 of the control byte functions as the continuation bit.
In FIG. 8, a D/C bit is provided as a second high order bit of a control byte to determine which of a command or data follows.
The I2C bus protocol comprises, as the multi-master-bus, all formats and procedures in a system, enabling specifications for controlling the bus by a plurality of micro-controllers as masters, for example, and hence it has high application flexibility. However, since many requirements must be fulfilled to control specific ICs, it is not always convenient to use the I2C bus protocol.
Meanwhile, the serial transmission system has the advantage that the number of terminals can be reduced to a greater extent than that of a parallel transmission system. However, this serial transmission system is inferior in speed of data transmission. In the actual situation, for example, an increase in the size of a liquid crystal screen cause liquid crystal display drivers or the like to be faced with demands for high speed data transmission.
However, the outlined I2C bus protocol is limited in the speed-up of data transmission. This is because one byte including a slave address is required to be located at the top of each byte of a command and data, and an acknowledge bit A sent from a slave IC is always required subsequent to individual one byte information. Because the information transmitted between the master and the slave is increased in this manner, speed-up of data transmission is limited. Moreover, presence of the acknowledge bit A decreases the transfer rate of serial clock signals and restricts the speed-up of data transmission because of the following reasons.
FIG. 9 shows a signal line L of a serial data line SDA. A source voltage VCC is applied to the signal line L via a pull-up resistance R1 and the signal line L has its own wiring capacitance C. A switch SW consisting of a MOS transistor is disposed on the side of a slave IC. This switch SW is turned on to discharge the charge of the signal line L1 to thereby drop the potential to 0 V, supplying the aforementioned acknowledge bit A from the slave IC to a master micro-controller. A resistance R3 shown in FIG. 9 is a total resistance (such as an ITO wiring resistance and a connector resistance) from a terminal of the IC to a substrate. At this time, since the switch SW has an on-resistance R2, a time depending on the time constant decided by the resistance R1, R2, and R3 and the wiring capacitance C, is required for discharging the signal line L1. It is therefore necessary to determine the frequency of the serial clock signal on the basis of the time constant. This frequency is 100 kHz in a standard mode, about 400 kHz in a fast mode, and about 3.4 MHz even in a high-speed mode.
In a semiconductor-manufacturing process used to realize a high performance micro-controller, progress is being made in miniaturization. Source voltage is decreased to a lower voltage level corresponding to the miniaturization in the process.
With the decrease in source voltage, the on-resistance R2 of the switch SW formed by a MOS transistor for sending the acknowledge bit A of the slave IC is increased. The time constant for discharging the signal line L1 is thereby increased. This also hinders the speed-up of data transmission.
Moreover, the pull-up resistance R1 and the resistance (R2+R3) divide the voltage to create a 0 level for the acknowledge bit A. The larger the resistance (R2+R3), the higher the potential at the 0 level and the smaller an allowable noise margin.
In view of the above situation, it is an objective of the present invention to provide a display driver IC which adopts a serial transmission system to reduce the number of terminal pins, transmits a command and data efficiently, and also can deal with the speed-up of data transmission and a reduction in the voltage of interface signals, and to provide an electronic device using the display driver IC.
According to a first aspect of the present invention, there is provided a display driver IC comprising:
an interface circuit to which signals from an external MPU are input;
a command decoder for decoding command data input from the external MPU through the interface circuit;
a storage section in which display data input from the external MPU through the interface is written; and
a display driving section for driving a display on the basis of the display data written in the storage section,
wherein the interface circuit comprises:
a first input terminal to which one unit data column of (N+1) bits is input serially, the one unit data column including data groups of N bits which are simultaneously processed by the external MPU and identification data of one bit which identifies whether the data groups are groups of the command data or the display data;
a second input terminal to which a serial clock signal is input; and
a third input terminal to which a chip select signal is input.
According to this aspect of the present invention, when contents of the storage section in the display driver IC is changed, required signals can be transmitted to the display driver IC from the external MPU by using only the first to third input terminals. Namely, it is sufficient to serially transmit the command data, display data, and identification data for identifying the command data and display data from the external MPU to the display driver IC according to the serial clock signals after the display driver IC has been made to be accessible by the chip select signal.
A serial data input signal in this case has one unit data column of (N+1) bits, which consists of one bit identification data for the identifying the command data and display data and N-bit command or display data. Accordingly, as to the number of bits of the command data and display data, N bits which are simultaneously processed by the external MPU may be allotted.
In addition, unlike the foregoing I2C bus protocol, it is unnecessary for this display driver IC to send the acknowledge bit A every time data of N bits is input from the external MPU. It is therefore unnecessary to pull up a signal line to be connected to the first input terminal and to discharge the signal line so that the potential of the signal line becomes LOW every time information of N bits is input. It is hence possible to speed-up data transmission.
In this display driver IC, the interface circuit may comprise:
a frequency dividing circuit which divides a frequency of the serial clock signal in 1/(N+1) when the chip select signal is active;
an (N+1) bit shift register which sequentially shifts each bit data in the one unit data column of (N+1) bits on the basis of the serial clock signal and outputs the each bit data in the one unit data column of (N+1) bits in parallel when the chip select signal is active; and
an (N+1) bit latch circuit which latches the one unit data column of (N+1) bits on the basis of the output of the frequency dividing circuit.
This structure enables data of (N+1) bits which is input serially to be subjected to serial-parallel conversion and the date to be latched onto every unit data column of (N+1) bits.
The command decoder may generate a timing signal which is supplied for writing the display data into the storage section, on the basis of the output of the frequency dividing circuit.
For instance, the command decoder can generate write signals on the basis of the output from the frequency dividing circuit, so that the supply of a write command from the external MPU is not required. Therefore, the load on the external MPU can be reduced and signal lines and input terminals for write signals can be omitted.
Moreover, the chip select signal may have a pulse which is non-active between continuous two unit data columns each having (N+1) bits during an active period. The frequency dividing circuit and the (N+1) bit shift register may be reset by this pulse.
Data can be latched by the (N+1) bit latch circuit on the basis of the output from the frequency dividing circuit in this manner, thus preventing an erroneous recognition of the border between unit data columns of (N+1) bits. As a result, a data transmission error can be reduced.
According to a second aspect of the present invention, there is provided an electronic device comprising:
the aforementioned display driver IC;
an MPU which supplies a chip select signal, a serial data input signal and a serial clock signal to the display driver IC; and
a display section which is controlled by the display driver IC.
In this electronic device, only three pins are necessary for the external MPU to rewrite display data in the display driver IC, with the other pins being made available for other circuits to be controlled.